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PEB2256HT Datasheet(PDF) 235 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 235 Page - Infineon Technologies AG |
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235 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 235 2002-08-27 Transmit Spare Bits (Read/Write) Value after reset: 00 H CASEN Channel Associated Signaling Enable 0 = Normal operation. 1 = A one in this bit position causes the transmitter to send the CAS information stored in the XS(16:1) registers or serial CAS data in the corresponding time slots. TT0 Time slot 0 Transparent Mode 0 = Normal operation. 1 = All information for time slot 0 on port XDI is inserted in the outgoing pulseframe. All internal information of the FALC56 (framing, CRC, S a/Si-bit signaling, remote alarm) is ignored. This function is mainly useful for system test applications (test loops). Priority sequence of transparent modes: XSP.TTO > TSWM. EBP E-Bit Polarity 0 = In the basic- and multiframe asynchronous state the E-bit is cleared. 1 = In the basic- and multiframe asynchronous state the E-bit is set. If automatic transmission of submultiframe status is enabled by setting bit XSP.AXS and the receiver has lost synchronization, the E-bit with the programmed polarity is inserted automatically in S i-bit position of every outgoing CRC multiframe (under the condition that time slot 0 transparent mode and transparent S i bit in service word are both disabled). AXS Automatic Transmission of Submultiframe Status Only applicable to CRC multiframe. 0 = Normal operation. 1 = Information of submultiframe status bits RSP.SI1 and RSP.SI2 are inserted automatically in S i -bit positions of the outgoing CRC multiframe (RSP.SI1 → S i -bit of frame 13; RSP.SI2 → S i-bit of frame 15). Contents of XSP.XS13 and XSP.XS15 is 70 XSP CASEN TT0 EBP AXS XSIF XS13 XS15 (21) |
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