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PEB2256HT Datasheet(PDF) 236 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 236 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
236
2002-08-27
ignored. If one of the time slot 0 transparent modes XSP.TT0 or
TSWM.TSIS is enabled, bit XSP.AXS has no function.
XSIF
Transmit Spare Bit For International Use (FAS Word)
First bit in the FAS word. Only significant in doubleframe format. If not
used, this bit should be fixed to "1". If one of the time slot 0 transparent
modes is enabled (bits XSP.TT0, or TSWM.TSIF), bit XSP.XSIF is
ignored.
XS13
Transmit Spare Bit (Frame 13, CRC-Multiframe)
First bit in the service word of frame 13 for international use. Only
significant in CRC-multiframe format. If not used, this bit should be
fixed to "1". The information of XSP.XS13 is shifted into internal
transmission buffer with beginning of the next following transmitted
CRC multiframe.
If automatic transmission of submultiframe status is enabled by bit
XSP.AXS, or, if one of the time slot 0 transparent modes XSP.TT0 or
TSWM.TSIS is enabled, bit XSP.XS13 is ignored.
XS15
Transmit Spare Bit (Frame 15, CRC-Multiframe)
First bit in the service word of frame 15 for international use. Only
significant in CRC-multiframe format. If not used, this bit should be
fixed to "1". The information of XSP.XS15 is shifted into the internal
transmission buffer with beginning of the next following transmitted
CRC multiframe.
If automatic transmission of submultiframe status is enabled by bit
XSP.AXS, or, if one of the time slot 0 transparent modes XSP.TT0 or
TSWM.TSIF is enabled, bit XSP.XS15 is ignored.
Transmit Control 0 (Read/Write)
Value after reset: 00
H
SA(8:4)E
S
a-Bit Signaling Enable
0 =
Standard operation.
1 =
Setting this bit makes it possible to send/receive a LAPD
protocol in any combination of the S
a-bit positions in the
outgoing/incoming data stream. The on chip signaling controller
has to be configured in the HDLC/LAPD mode. In transmit
70
XC0
SA8E
SA7E
SA6E
SA5E
SA4E
XCO10
XCO9
XCO8
(22)



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