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PEB2256HT Datasheet(PDF) 234 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 234 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
234
2002-08-27
Transmit Service Word Pulseframe (Read/Write)
Value after reset: 00
H
XSIS
Spare Bit For International Use
First bit of the service word. Only significant in doubleframe format. If
not used, this bit should be fixed to "1". If one of the time slot 0
transparent modes is enabled (bit XSP.TT0, or TSWM.TSIS), bit
XSW.XSIS is ignored.
XTM
Transmit Transparent Mode
0 =
Ports SYPX/XMFS define the frame/multiframe begin on the
transmit
system
highway.
The
transmitter
is
usually
synchronized on this externally sourced frame boundary and
generates the FAS-bits according to this framing. Any change
of the transmit time slot assignment subsequently produces a
change of the FAS-bit positions.
1 =
Disconnects the control of the transmit system interface from
the transmitter. The transmitter is now in a free running mode
without any possibility to actualize the multiframe position. The
framing (FAS-bits) generated by the transmitter is not
“disturbed” (in case of changing the transmit time slot
assignment) by the transmit system highway unless register
XC1 is written. Useful in loop-timed applications. For proper
operation
the
transmit
elastic
buffer
(2
frames,
SIC1.XBS(1:0) = 10) has to be enabled.
XRA
Transmit Remote Alarm
0 =
Normal operation.
1 =
Sends remote alarm towards remote end by setting bit 3 of the
service word. If time slot 0 transparent mode is enabled by bit
XSP.TT0 or TSWM.TRA bit is set, bit XSW.XRA is ignored.
XY(4:0)
Spare Bits For National Use (Y-Bits, Sn-Bits, Sa-Bits)
These bits are inserted in the service word of every other pulseframe
if Sa-bit register access is disabled (FMR1.ENSA = 0). If not used,
they should be fixed to “1”.
If one of the time slot 0 transparent modes is enabled (bit XSP.TT0 or
TSWM.TSA(8:4)), bits XSW.XY(4:0) are ignored.
70
XSW
XSIS
XTM
XRA
XY0
XY1
XY2
XY3
XY4
(20)



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