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PEB2256HT Datasheet(PDF) 263 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 263 Page - Infineon Technologies AG |
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263 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 263 2002-08-27 Transmit CAS Register (Write) Value after reset: not defined Transmit CAS Register (16:1) The transmit CAS register access is enabled by setting bit XSP.CASEN = 1. Each register except XS1 contains the CAS bits for two time slots. With the transmit multiframe begin ISR1.XMB the contents of these registers is copied into a shadow register. The contents is sent out subsequently in the time slots 16 of the outgoing data stream. Note: If ISR1.XMB is not used and the write access to these registers is done exact in the moment when this interrupt is generated, data is lost. XS1.7 is sent out first and XS16.0 is sent last. The transmit multiframe begin interrupt (XMB) requests that these registers should be serviced. If requests for new information are ignored, current contents is repeated. XS1 has to be programmed with the multiframe pattern. This pattern should always stay low otherwise the remote end loses its synchronization. With setting the Y-bit a remote alarm is transmitted to the far end. The X bits (spare bits) should be set if they are not used. Table 59 Transmit CAS Registers (E1) 70 XS1 00 00 X Y X X (70) XS2 A1 B1 C1 D1 A16 B16 C16 D16 (71) XS3 A2 B2 C2 D2 A17 B17 C17 D17 (72) XS4 A3 B3 C3 D3 A18 B18 C18 D18 (73) XS5 A4 B4 C4 D4 A19 B19 C19 D19 (74) XS6 A5 B5 C5 D5 A20 B20 C20 D20 (75) XS7 A6 B6 C6 D6 A21 B21 C21 D21 (76) XS8 A7 B7 C7 D7 A22 B22 C22 D22 (77) XS9 A8 B8 C8 D8 A23 B23 C23 D23 (78) XS10 A9 B9 C9 D9 A24 B24 C24 D24 (79) XS11 A10 B10 C10 D10 A25 B25 C25 D25 (7A) XS12 A11 B11 C11 D11 A26 B26 C26 D26 (7B) XS13 A12 B12 C12 D12 A27 B27 C27 D27 (7C) XS14 A13 B13 C13 D13 A28 B28 C28 D28 (7D) XS15 A14 B14 C14 D14 A29 B29 C29 D29 (7E) XS16 A15 B15 C15 D15 A30 B30 C30 D30 (7F) |
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