PEB2256HT datasheet(266/490 Pages) INFINEON

266 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

266

2002-08-27

highway. Optionally sampling of XSIG data is controlled by

the active high XSIGM marker.

0011 = TCLK: Transmit Clock (Input)

A 2.048/8.192 MHz clock has to be sourced by the system if

the internal generated transmit clock (DCO-X) is not used.

Optionally this input is used as a synchronization clock for the

DCO-X circuitry with a frequency of 2.048 MHz.

0100 = XMFB: Transmit Multiframe Begin (Output)

Marks the beginning of every transmit multiframe.

0101 = XSIGM: Transmit Signaling Marker (Output)

Marks the time slots which are defined by register TTR(4:1) of

every frame on port XDI.

0110 = DLX: Data Link Bit Transmit (Output)

Marks the S

a-bits within the data stream on XDI.

0111 = XCLK: Transmit Line Clock (Output)

Frequency: 2.048 MHz

1000 = XLT: Transmit Line Tristate (Input)

With a high level on this port the transmit lines XL1/2 or

XDOP/N are set directly into tristate. This pin function is

logically ored with register XPM2.XLT.

Port Configuration 5 (Read/Write)

Value after reset: 00H

CCLK2

Configure CLK2 Port

0 =

CLK2 is input

1 =

CLK2 is output (only, if DCO-X is active)

CCLK1

Configure CLK1 Port

0 =

CLK1 is input

1 =

CLK1 is output (only, if DCO-R is active)

PC5

CCLK2

CCLK1

CXMFS

CSRP

CRP

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