PEB2256HT datasheet(269/490 Pages) INFINEON

269 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

269

2002-08-27

Command Register 2 (Write)

Value after reset: 00

RSUC

Reset Signaling Unit Counter

After setting this bit the SS7 signaling unit counter and error counter

are reset.The bit is cleared automatically after execution.

Note: The maximum time between writing to the CMDR2 register

and the execution of the command takes 2.5 periods of the

current system data rate. Therefore, if the CPU operates with

a very high clock rate in comparison with the FALC56's clock,

it is recommended that bit SIS.CEC should be checked before

writing to the CMDR2 register to avoid any loss of commands.

Command Register 3 (Write)

Value after reset: 00

RMC2

Receive Message Complete - HDLC Channel 2

Confirmation from CPU to FALC

® that the current frame or data block

has been fetched following an RPF2 or RME2 interrupt, thus the

occupied space in the RFIFO2 can be released.

XREP2

Transmission Repeat - HDLC Channel 2

If XREP2 is set together with XTF2 (write 24H to CMDR3), the FALC

repeatedly transmits the contents of the XFIFO2 (1 to 32 bytes)

without HDLC framing fully transparently, i.e. without flag, CRC.

The cyclic transmission is stopped with an SRES2 command or by

resetting XREP2.

XHF2

Transmit HDLC Frame - HDLC Channel 2

After having written up to 32 bytes to the XFIFO2, this command

initiates the transmission of a HDLC frame.

CMDR2

RSUC

(x87)

CMDR3

RMC2

XREP2

XHF2

XTF2

XME2

SRES2

(88)

PEB2256HT Datasheet(PDF) 269 Page - Infineon Technologies AG

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