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PEB2256HT Datasheet(PDF) 270 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 270 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
270
2002-08-27
XTF2
Transmit Transparent Frame - HDLC Channel 2
Initiates the transmission of a transparent frame without HDLC
framing.
XME2
Transmit Message End - HDLC Channel 2
Indicates that the data block written last to the XFIFO2 completes the
current frame. The FALC
® can terminate the transmission operation
properly by appending the CRC and the closing flag sequence to the
data.
SRES2
Signaling Transmitter Reset - HDLC Channel 2
The transmitter of the signaling controller is reset. XFIFO2 is cleared
of any data and an abort sequence (seven 1s) followed by interframe
time fill is transmitted. In response to SRES2 an XPR2 interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Command Register 4 (Write)
Value after reset: 00
H
RMC3
Receive Message Complete - HDLC Channel 3
Confirmation from CPU to FALC
® that the current frame or data block
has been fetched following an RPF3 or RME3 interrupt, thus the
occupied space in the RFIFO3 can be released.
XREP3
Transmission Repeat - HDLC Channel 3
If XREP3 is set together with XTF3 (write 24H to CMDR4), the FALC
®
repeatedly transmits the contents of the XFIFO3 (1 to 32 bytes)
without HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with an SRES3 command or by
resetting XREP3.
XHF3
Transmit HDLC Frame - HDLC Channel 3
After having written up to 32 bytes to the XFIFO3, this command
initiates the transmission of a HDLC frame.
70
CMDR4
RMC3
XREP3
XHF3
XTF3
XME3
SRES3
(89)



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