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PEB2256HT Datasheet(PDF) 268 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 268 Page - Infineon Technologies AG |
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268 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 268 2002-08-27 Port Configuration 6 (Read/Write) Value after reset: 00H SXCL(1:0) Select Transmit Clock Frequency on Port CLK2 Port CLK2 is the de-jittered DCO-X clock at a frequency of 00 = 2.048 MHz 01 = 4.096 MHz 10 = 8.192 MHz 11 = 16.384 MHz Note: If DCO-X is not used, no clock is output on pin CLK2 (SIC1.XBS(1:0)=00 and CMR1.DXJA=1; buffer bypass and no jitter attenuation) SCL(2:0) Select System Clock Frequency on Port CLK1 Port CLK1 is the de-jittered DCO-R clock at a frequency of 000 = 8 kHz 001 = 2.048 MHz 010 = 4.096 MHz 011 = 8.192 MHz 100 = 16.384 MHz 101 to 111 = Not defined Note: If DCO-R is not active, no clock is output on pin CLK1 (SIC1.RBS(1:0)=11 and CMR1.RS1=0). 70 PC6 SXCL1 SXCL0 SCL2 SCL1 SCL0 (86) |
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