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PEB2256HT Datasheet(PDF) 271 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 271 Page - Infineon Technologies AG |
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271 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 271 2002-08-27 XTF3 Transmit Transparent Frame - HDLC Channel 3 Initiates the transmission of a transparent frame without HDLC framing. XME3 Transmit Message End - HDLC Channel 3 Indicates that the data block written last to the XFIFO3 completes the current frame. The FALC ® can terminate the transmission operation properly by appending the CRC and the closing flag sequence to the data. SRES3 Signaling Transmitter Reset - HDLC Channel 3 The transmitter of the signaling controller is reset. XFIFO3 is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. In response to SRES3 an XPR3 interrupt is generated. This command can be used by the CPU to abort a frame currently in transmission. Common Configuration Register 3 (Read/Write) Value after reset: 00 H RADD2 Receive Address Pushed to RFIFO2 If this bit is set, the received HDLC channel 2 address information (1 or 2 bytes, depending on the address mode selected via MODE2.MDS02) is pushed to RFIFO2. This function is applicable in non-auto mode and transparent mode 1. RCRC2 Receive CRC ON/OFF - HDLC Channel 2 Only applicable in non-auto mode. If this bit is set, the received CRC checksum is written to RFIFO2 (CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in the received frame, is followed in the RFIFO2 by the status information byte (contents of register RSIS2). The received CRC checksum will additionally be checked for correctness. If non-auto mode is selected, the limits for “Valid Frame” check are modified. 70 CCR3 RADD2 RCRC2 XCRC2 ITF2 XMFA2 RFT12 RFT02 (8B) |
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