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PEB2256HT Datasheet(PDF) 273 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 273 Page - Infineon Technologies AG |
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273 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 273 2002-08-27 Common Configuration Register 4 (Read/Write) Value after reset: 00 H RADD3 Receive Address Pushed to RFIFO3 If this bit is set, the received HDLC channel 3 address information (1 or 2 bytes, depending on the address mode selected via MODE3.MDS03) is pushed to RFIFO3. This function is applicable in non-auto mode and transparent mode 1. RCRC3 Receive CRC ON/OFF - HDLC Channel 3 Only applicable in non-auto mode. If this bit is set, the received CRC checksum is written to RFIFO3 (CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in the received frame, is followed in the RFIFO3 by the status information byte (contents of register RSIS3). The received CRC checksum will additionally be checked for correctness. If non-auto mode is selected, the limits for “Valid Frame” check are modified. XCRC3 Transmit CRC ON/OFF - HDLC Channel 3 If this bit is set, the CRC checksum will not be generated internally. It has to be written as the last two bytes in the transmit FIFO (XFIFO3). The transmitted frame is closed automatically with a closing flag. ITF3 Interframe Time Fill - HDLC Channel 3 Determines the idle (= no data to be sent) state of the transmit data coming from the signaling controller. 0 = Continuous logical "1" is output 1 = Continuous flag sequences are output ("01111110" bit patterns) XMFA3 Transmit Multiframe Aligned - HDLC Channel 3 Determines the synchronization between the framer and the corresponding signaling controller. 0 = The contents of the XFIFO3 is transmitted without multiframe alignment. 1 = The contents of the XFIFO3 is transmitted multiframe aligned. 70 CCR4 RADD3 RCRC3 XCRC3 ITF3 XMFA3 RFT13 RFT03 (8C) |
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