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PEB2256HT Datasheet(PDF) 276 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 276 Page - Infineon Technologies AG |
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276 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 276 2002-08-27 Mode Register 3 (Read/Write) Value after reset: 00 H MDS3(2:0) Mode Select - HDLC Channel 3 The operating mode of the HDLC controller is selected. 000 =Reserved 001 =Reserved 010 =One-byte address comparison mode (RAL1, 2) 011 =Two-byte address comparison mode (RAH1, 2 and RAL1, 2) 100 =No address comparison 101 =One-byte address comparison mode (RAH1, 2) 110 =Reserved 111 =No HDLC framing mode 1 HRAC3 Receiver Active - HDLC Channel 3 Switches the HDLC receiver to operational or inoperational state. 0 = Receiver inactive 1 = Receiver active DIV3 Data Inversion - HDLC Channel 3 Setting this bit will invert the internal generated HDLC data stream. 0 = Normal operation, HDLC data stream not inverted 1 = HDLC data stream inverted 70 MODE3 MDS32 MDS31 MDS30 HRAC3 DIV3 (8F) |
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