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PEB2256HT Datasheet(PDF) 279 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 279 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
279
2002-08-27
Global Clock Mode Register 5 (Read/Write)
Value after reset: 00
H
MCLK_LOW
Master Clock Range Low
0 =
Master clock frequency divided by (PLL_M+1) is greater than or
equal 1.5 MHz
1 =
Master clock frequency divided by (PLL_M+1) is less than 1.5
MHz
PLL_M(4:0)
PLL Dividing Factor M
For details see calculation formulas below.
Note: Write operations to GCM5 initiate a PLL reset (see below).
Global Clock Mode Register 6 (Read/Write)
Value after reset: 00
H
PLL_N(4:0)
PLL Dividing Factor N
For details see calculation formulas below.
Note: Write operations to GCM6 initiate a PLL reset (see below).
70
GCM5
MCLK_
LOW
PLL_M
4
PLL_M
3
PLL_M
2
PLL_M
1
PLL_M
0
(96)
70
GCM6
PLL_N
4
PLL_N
3
PLL_N
2
PLL_N
1
PLL_N
0
(97)



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