PEB2256HT datasheet(282/490 Pages) INFINEON

282 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

282

2002-08-27

EO1(1:0)

Even/Odd frame selection HDLC Channel 1

Channel 1 HDLC protocol data can be sent in even, odd or both

frames of a multiframe.

00 = Even and odd frames

01 = Odd frames only

10 = Even frames only

11 = Undefined

EO2(1:0)

Even/Odd frame selection HDLC Channel 2

Channel 2 HDLC protocol data can be sent in even, odd or both

frames of a multiframe.

00 = Even and odd frames

01 = Odd frames only

10 = Even frames only

11 = Undefined

EO3(1:0)

Even/Odd frame selection HDLC Channel 3

Channel 3 HDLC protocol data can be sent in even, odd or both

frames of a multiframe.

00 = Even and odd frames

01 = Odd frames only

10 = Even frames only

11 = Undefined

Time Slot Bit Select 1 (Read/Write)

Value after reset: FF

TSB1(7:0)

Time Slot Bit Selection - HDLC Channel 1

Only bits selected by this register are used for HDLC channel 1 in

selected time slots. Time slot selection is done by setting the

appropriate bits in registers TTR(4:1) and RTR(4:1) independently

for receive and transmit direction. Bit selection is common to receive

and transmit direction. By default all bit positions within the selected

time slot(s) are enabled.

0 = Bit position x in selected time slot(s) is not used for HDLC

channel 1 reception and transmission.

TSBS1

TSB17

TSB16

TSB15

TSB14

TSB13

TSB12

TSB11

TSB10

(A1)

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