PEB2256HT datasheet(280/490 Pages) INFINEON

280 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

280

2002-08-27

Flexible Clock Mode Settings

If flexible master clock mode is used (VFREQ_EN = 1), the according register settings

can be calculated as follows (a windows-based program for automatic calculation is

available, see Chapter 13.3 on page 481). For some of the standard frequencies see

the table below.

1. PLL_M and PLL_N must fulfill the equations:

a. 1.5 MHz

≤ f

MCLK / (PLL_M+1) ≤ 2.048 MHz

b. If (a.) is not possible, set MCLK_LOW and fulfill

1.02 MHz

≤ f

MCLK /(PLL_M+1) ≤ 1.5 MHz

c. 65 MHz

≤ f

MCLK × (2×PLL_N+2) / (PLL_M+1) ≤ 69.7 MHz

(as high as possible within this range)

2. Selection of dividing mode to best fulfill:

outE1 =( fMCLK × (2×PLL_N+2) / (PLL_M+1) ) / DIV_E1 (target E1: 16.384 MHz)

outT1 =( fMCLK × (2×PLL_N+2) / (PLL_M+1) ) / DIV_T1 (target T1: 12.352 MHz)

Though the target frequency might not be met directly, the dividing mode has to be

selected to reach a frequency, which is as near as possible to the target frequency.

3. Calculation of correction value (frequency mismatch correction)

PHD_E1 = 6

× 4096 × [DIV_E1 - (2×PLL_N+2)/(PLL_M+1) × (f

MCLK/16.384 MHz)]

PHD_T1 = 6

× 4096 × [DIV_T1 - (2×PLL_N+2)/(PLL_M+1) × (f

MCLK/12.352 MHz)]

The result of these equations will be in the range of -2048 to +2047. Negative values are

represented in 2s-complement format (e.g. -2000

D = 830H; +2000D =7D0H).

Table 60

Clock Mode Register Settings for E1 or T1/J1

MCLK [MHz]

GCM1

GCM2

GCM3

GCM4

GCM5

GCM6

1.544

F0H

51H

00H

80H

00H

15H

2.048

8.192

10.000

12.352

F0H

51H

00H

80H

07H

15H

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