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PEB2256HT Datasheet(PDF) 278 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 278 Page - Infineon Technologies AG |
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278 / 490 page ![]() FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 278 2002-08-27 Global Clock Mode Register 3 (Read/Write) Value after reset: 00 H PHD_T1(7:0) Frequency Adjust for T1 For details see calculation formulas below. Global Clock Mode Register 4 (Read/Write) Value after reset: 00 H PHD_T1(8:11) Frequency Adjust for T1 For details see calculation formulas below. DVM_T1(0:2) Divider Mode for T1 000 = Not valid 001 = Divide by DIV_T1 = 3 010 = Divide by DIV_T1 = 4 1/6 011 = Divide by DIV_T1 = 4 100 = Divide by DIV_T1 = 5.5 101 = Divide by DIV_T1 = 5 1/3 110 = Divide by DIV_T1 = 5 2/3 111 = Not valid GCM4.4 Reserved Must be cleared. 70 GCM3 PHD_T1 7 PHD_T1 6 PHD_T1 5 PHD_T1 4 PHD_T1 3 PHD_T1 2 PHD_T1 1 PHD_T1 0 (94) 70 GCM4 DVM_T1 2 DVM_T1 1 DVM_T1 0 0 PHD_T1 11 PHD_T1 10 PHD_T1 9 PHD_T1 8 (95) |
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