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PEB2256HT Datasheet(PDF) 277 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 277 Page - Infineon Technologies AG |
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277 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 277 2002-08-27 Global Clock Mode Register 1 (Read/Write) Value after reset: 00 H PHD_E1(7:0) Frequency Adjust for E1 For details see calculation formulas below. Global Clock Mode Register 2 (Read/Write) Value after reset: 00 H PHD_E1(8:11) Frequency Adjust for E1 For details see calculation formulas below. VFREQ_EN Variable Frequency Enable 0 = Fixed clock frequency of 2.048 (E1) or 1.544 MHz (T1/J1) 1 = Variable master clock frequency DVM_E1(0:2) Divider Mode for E1 000 = Not valid 001 = Divide by DIV_E1 = 3 010 = Divide by DIV_E1 = 4 1/6 011 = Divide by DIV_E1 = 4 100 = Divide by DIV_E1 = 5.5 101 = Divide by DIV_E1 = 5 1/3 110 = Divide by DIV_E1 = 5 2/3 111 = Not valid 70 GCM1 PHD_E1 7 PHD_E1 6 PHD_E1 5 PHD_E1 4 PHD_E1 3 PHD_E1 2 PHD_E1 1 PHD_E1 0 (92) 70 GCM2 DVM_E1 2 DVM_E1 1 DVM_E1 0 VFREQ_ EN PHD_E1 11 PHD_E1 10 PHD_E1 9 PHD_E1 8 (93) |
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