Z80 datasheet(303/330 Pages) ZILOG

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Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

283

Sync Character Load Inhibit (D1)

Sync characters preceding the message (leading sync characters) are not

loaded into the receive buffers if this option is selected. Because CRC

calculations are not stopped by sync character stripping, this feature should

be enabled only at the beginning of the message.

Address Search Mode (D2)

If SDLC is selected, no receive interrupts can occur in the Address Search

mode without an address match. Therefore, messages containing addresses

that do not match the programmed address in WR6 or the global (1111

1111

) are rejected.

Receiver CRC Enable (D3)

If this bit is set, CRC calculation starts or restarts at the beginning of the last

character transferred from the receive shift register to the buffer stack. This

start or restart occurs regardless of the number of characters in the stack.

For more information about setting this bit, see “SDLC Receive CRC

Checking” (SDLC Receive section) and “CRC Error Checking”

(Synchronous Receive section).

Enter Hunt Phase (D4)

The Z80 SIO automatically enters the Hunt phase after a reset. However, it

can be re-entered if character synchronization is lost (Synchronous mode)

or if the contents of an incoming message are not needed (SDLC mode).

The Hunt phase is reentered by writing a 1 to bit D4. This sets the Sync/

Hunt bit (D4) in RR0.

Auto Enables(D5)

If this mode is selected, DCD and CTS become the receiver and transmitter

enables, respectively. If this bit is not set, DCD and CTS are simply inputs

to their corresponding status bits in RR0.

Z80 Datasheet(PDF) 303 Page - Zilog, Inc.