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Z80 Datasheet(PDF) 307 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 307 Page - Zilog, Inc. |
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307 / 330 page ![]() Z80 CPU Peripherals User Manual UM008101-0601 Serial Input/Output 287 used for both the receiver and transmitter. The system clock in all modes must be set to at least 4.5 times the data rate. If the x1 clock rate is selected, bit synchronization must be performed externally. Write Register 5 WR5 contains control bits that affect the operation of transmitter, with the exception of D2, which affects the transmitter and receiver. Transmit CRC Enable (D0) This bit determines if CRC is calculated on a specific transmit character. If it is set at the time the character is loaded from the transmit buffer into the transmit shift register, CRC is calculated on the character. CRC is not auto- matically sent unless this bit is set when the Transmit Underrun condition occurs. Table 25. Clock Rate Clock Rate 1 Clock Rate 0 Result 0 0 Data Rate x1 = Clock Rate 0 1 Data Rate x16 = Clock Rate 1 0 Data Rate x32 = Clock Rate 1 1 Data Rate x64 = Clock Rate Table26. WriteRegister5 TransmitterControl D7 D6 D5 D4 D3 D2 D1 DO DTR Tx Bits/ Char 1 Tx Bits/ Char 0 Send Break Tx Enable CRC-16/ SDLC RTS Tx CRC Enable |
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