Z80 datasheet(305/330 Pages) ZILOG

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Z80 CPU Peripherals

User Manual

UM008101-0601

Serial Input/Output

285

Parity (D0)

If this bit is set, an additional bit position is added to transmitted data and is

expected in receive data. This added bit position is in addition to those bits

specified in the bits/character control. In the Receive mode, the parity bit

received is transferred to the CPU as part of the character, unless eight bits/

character is selected.

Parity Even/Odd (D1)

If parity is specified, this bit determines whether the bit is sent and checked

as even or odd (1 = even).

Stop Bits0and 1(D2 and D3)

These bits determine the number of stop bits added to each asynchronous

character sent. The receiver always checks for one stop bit. A special mode

(00) designates that a synchronous mode is to be selected.

Table 22. Write Register 4 Rx and Tx Control

Clock

Rate 1

Clock

Rate 0

Sync

Modes 1

Sync

Modes 0

Stop

Bits 1

Stop

Bits 0

Parity

Even/

Odd

Parity

Table 23. Stop Bits

Stop Bits 1

Stop Bits 0

Result

Sync modes

1 stop bit per character

1-1/2 stop bits per character

2 stop bits per character

Z80 Datasheet(PDF) 305 Page - Zilog, Inc.

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