AD7779 datasheet(39/97 Pages) AD

39 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 39 of 97

ADC

DATA

SERIAL

INTERFACE

SPI

CONTROL

INTERFACE

FPGA

DSP

AVDD 3.3V

AVSSx

AIN7+

AIN7–

AIN0+

AIN0–

PGA

VCM

AVDD1x

BUFFER

FULL BUFFER

BUFFER

AD7779

DREGCAP

CONVST_SAR

GPIO2

GPIO0

REFx+

REFx–

REF_OUT

AVDD4

AVSSx

AVDD2x

AVDD3.3V

IOVDD 2V TO 3.6V

AVSSx

AREGxCAP

AVSSx

IOVDD

AUXAIN+

AUXAIN–

24-BIT

Σ-∆

ADC

12-BIT

SAR ADC

MUX

DIAGNOSTIC

INPUTS

SINC3/SRC

SYNC_IN

DRDY

SYNC_OUT

START

RESET

DCLK

SCLK

SDO

SDI

CLK_SEL

FORMAT0

XTAL2

FORMAT1

IOVDD

XTAL1

DOUT0

DOUT1

SPI/SPORT

SLAVE

INTERFACE

DOUT2

DOUT3

SPI

MASTER

INTERFACE

PGA

VCM

CLOCK

SOURCE

Figure 98. SPI Control Mode Connection Diagram with Internal Reference

SPI CONTROL

The second option for control and monitoring the AD7779 is via

the SPI interface. This option allows access to the full functionality

on the AD7779, including access to the SAR converter, phase

synchronization, offset and gain adjustment, diagnostics and

the SRC. To use the SPI control, set the FORMAT0 and

FORMAT1 pins to logic high.

In this mode, the SPI interface can also be used to read the -Δ

conversation data by setting the SPI_SLAVEMODE_EN bit.

The typical connection diagram for SPI control mode is shown

in Figure 98.

Functionality Available in SPI Mode

SPI control of the AD7779 offers the super set of the functions

and diagnostics. The SPI Control Functionality section describes

the functionality and diagnostics offered when in SPI control

mode.

Offset and Gain Correction

Offset and gain registers are available for system calibration.

The gain register is preprogrammed during final production for

a PGA gain of 1, but can be overwritten with a new value if

required.

The gain register is 24 bits long and is split across three registers,

CHx_GAIN_UPPER_BYTE, CHx_GAIN_MID_BYTE, and

CHx_GAIN_LOWER_BYTE, which set the gain on a per

channel basis.

The gain value is relative to 0x555555, which represents a gain of 1.

The offset register is 24 bits long and is spread across three byte

registers, CHx_OFFSET_UPPER_BYTE, CHx_OFFSET_MID_

BYTE, and CHx_OFFSET_LOWER_BYTE. The default value is

0x000000 at power-up. Program the offset as a twos complement,

signed 24-bit number. If the channel gain is set to its nominal

value of 0x555555, an LSB of offset register adjustment changes

the digital output by −4/3 LSBs.

As an example of calibration, the offset measured is −200 LSB

(with both AINx± pins connected to the same potential).

An offset adjustment of −150 changes the digital output by

−150 × (−4/3) = 200 LSBs (gain value = 0x555555), representing

this number as two complement, 0xFFFFFF – 0x96 + 1 =

0xFFFF70.



CHx_OFFSET_UPPER_BYTE = 0xFF



CHx_OFFSET_MID_BYTE = 0xFF



CHx_OFFSET_LOWER_BYTE = 0x70

Note that the offset compensation is performed before the gain

compensation. The gain is programmed during final testing for

PGAGAIN = 1. The gain register values can be overwritten; however,

after a reset or power cycle, the gain register values revert to the

hard coded programmed factory setting.

If the gain required is 0.75 of the nominal value (0x555555), the

value that must be programmed is

0x555555 × 0.75 = 0x400000

Then, an LSB of the offset register adjustment changes the

digital output by −4/3 × 0.75 = 1 LSB.



CHx_GAIN_UPPER_BYTE = 0x40



CHx_GAIN_MID_BYTE = 0x00



CHx_GAIN_LOWER_BYTE = 0x00

AD7779 Datasheet(PDF) 39 Page - Analog Devices

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