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AD7779 Datasheet(PDF) 11 Page - Analog Devices

Part # AD7779
Description  8-Channel, 24-Bit, Simultaneous Sampling ADC
PDF  97 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7779 Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
AD7779
Rev. 0 | Page 11 of 97
SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS
AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− =
2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Description1
Test Conditions/Comments
Min
Typ
Max
Unit
t26
START Setup Time
10
ns
t27
START Hold Time
MCLK
ns
t28
MCLK Falling Edge to SYNC_OUT Falling Edge
MCLK
ns
t29
SYNC_IN Setup Time
10
ns
t30
SYNC_IN Hold Time
MCLK
ns
tINIT_
SYNC_IN
SYNC_IN Rising Edge to First DRDY
16 kSPS, HP mode
145
μs
tINIT_
RESET
RESET Rising Edge to First DRDY
16 kSPS, HP mode
225
μs
t31
RESET Hold Time
2 × MCLK
ns
tPOWER_UP
Start Time
tPOWER_UP is not shown in Figure 4
2
ms
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
START
SYNC_OUT
SYNC_IN
DRDY
RESET
t26
t27
t28
t29
tINIT_SYNC_IN
t31
tINIT_RESET
t30
Figure 4. Synchronization Pins and Reset Control Interface Timing Diagram



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