AD7779 datasheet(78/97 Pages) AD

78 / 97 page

AD7779

Data Sheet

Rev. 0 | Page 78 of 97

CHANNEL 3 OFFSET UPPER BYTE REGISTER

Address: 0x02E, Reset: 0x00, Name: CH3_OFFSET_UPPER_BYTE

Com bined offs et regis ter Channel 3

[7:0] CH3_OFFSET_ALL[23:16] (R/W)

Table 89. Bit descriptions for CH3_OFFSET_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_OFFSET_ALL[23:16]

Combined Offset Register Channel 3

0x0

R/W

CHANNEL 3 OFFSET MIDDLE BYTE REGISTER

Address: 0x02F, Reset: 0x00, Name: CH3_OFFSET_MID_BYTE

Com bined offs et regis ter Channel 3

[7:0] CH3_OFFSET_ALL[15:8] (R/W)

Table 90. Bit Descriptions for CH3_OFFSET_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_OFFSET_ALL[15:8]

Combined Offset Register Channel 3

0x0

R/W

CHANNEL 3 OFFSET LOWER BYTE REGISTER

Address: 0x030, Reset: 0x00, Name: CH3_OFFSET_LOWER_BYTE

Com bined offs et regis ter Channel 3

[7:0] CH3_OFFSET_ALL[7:0] (R/W)

Table 91. Bit Descriptions for CH3_OFFSET_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_OFFSET_ALL[7:0]

Combined Offset Register Channel 3

0x0

R/W

CHANNEL 3 GAIN UPPER BYTE REGISTER

Address: 0x031, Reset: 0x00, Name: CH3_GAIN_UPPER_BYTE

Com bined gain register Channel 3

[7:0] CH3_GAIN_ALL[23:16] (R/W)

Table 92. Bit Descriptions for CH3_GAIN_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_GAIN_ALL[23:16]

Combined Gain Register Channel 3

0x0

R/W

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