AD7779 datasheet(77/97 Pages) AD

77 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 77 of 97

CHANNEL 2 OFFSET LOWER BYTE REGISTER

Address: 0x02A, Reset: 0x00, Name: CH2_OFFSET_LOWER_BYTE

Com bined offs et regis ter Channel 2

[7:0] CH2_OFFSET_ALL[7:0] (R/W)

Table 85. Bit Descriptions for CH2_OFFSET_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_OFFSET_ALL[7:0]

Combined Offset Register Channel 2

0x0

R/W

CHANNEL 2 GAIN UPPER BYTE REGISTER

Address: 0x02B, Reset: 0x00, Name: CH2_GAIN_UPPER_BYTE

Com bined gain register Channel 2

[7:0] CH2_GAIN_ALL[23:16] (R/W)

Table 86. Bit Descriptions for CH2_GAIN_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_GAIN_ALL[23:16]

Combined Gain Register Channel 2

0x0

R/W

CHANNEL 2 GAIN MIDDLE BYTE REGISTER

Address: 0x02C, Reset: 0x00, Name: CH2_GAIN_MID_BYTE

Com bined gain register Channel 2

[7:0] CH2_GAIN_ALL[15:8] (R/W)

Table 87. Bit Descriptions for CH2_GAIN_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_GAIN_ALL[15:8]

Combined Gain Register Channel 2

0x0

R/W

CHANNEL 2 GAIN LOWER BYTE REGISTER

Address: 0x02D, Reset: 0x00, Name: CH2_GAIN_LOWER_BYTE

Com bined gain register Channel 2

[7:0] CH2_GAIN_ALL[7:0] (R/W)

Table 88. Bit Descriptions for CH2_GAIN_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_GAIN_ALL[7:0]

Combined Gain Register Channel 2

0x0

R/W

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