AD7779 datasheet(50/97 Pages) AD

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AD7779

Data Sheet

Rev. 0 | Page 50 of 97

SAMPLE RATE CONVERTER (SRC) (SPI CONTROL

MODE)

The AD7779 implements a patented featured called the SRC on

each -Δ channel, which allows the user to configure the output

data rate or sampling frequency to any desired value, including

noninteger values. The SRC achieves fine resolution control

over the -Δ ADC ODR, up to 15.2 μSPS. In applications where

the ODR must change based on changes in the input signal to

maintain sampling coherency, the SRC provides fine control

over the ODR. For example, to achieve the highest classification

standard, Class A, in power quality applications, coherency

must be maintained for 0.01 Hz changes in the input power

line. The SRC can be used to achieve this sampling frequency

accuracy.

In the pin control mode, the ODR is fixed per the predefined

pin control options. Consequently, a noninteger number cannot

be selected, as shown in Table 17.

To set the ODR, the user must program up to four registers,

depending on the decimation value: two registers to program

the integer value, N (the effective decimation rate), and two

registers to program the decimal value, IF (the inter-polation

factor).

The integer value registers are SRC_N_MSB, Bits[3:0] and

SRC_N_LSB, Bits[7:0]. The decimal part value registers are

SRC_IF_MSB, Bits[7:0] and SRC_IF_LSB, Bits[7:0].

As an example, if an output data rate of 2.8 kHz is required,

which equates to



HP mode = 2048/2.8 = 731.428



Low power mode = 512/2.8 = 182.857

The register values for HP mode are as follows:



731d = 0x2DB



SRC_N_MSB[3:0] = 0x02



SRC_N_LSB[7:0] = 0xDB



0.428d = 0.428 × 216 = 28049d = 0x6D91



SRC_IF_MSB[7:0] = 0x6D



SRC_IF_LSB[7:0] = 0x91

The ODR can be updated on the fly, but a new ODR is effective

in three conversion cycles of the -Δ ADCs. This guarantees a

smooth transition with no conversion results out of range.

There are two different ways to change the ODR after a new

value is written in the SRC registers: via software or via

hardware, depending on SRC_UPDATE, Bit 7.

If the SRC_LOAD_SOURCE bit is clear, the new ODR value is

updated by setting the SRC_LOAD_UPDATE bit to 1. This bit

must be held high for at least two MLCK periods; return the bit

to 0 before attempting another update.

If SRC_LOAD_SOURCE is set, the ODR update is controlled

externally by the GPIO0 pin. Apply a pulse in the GPIO2 pin,

which is then internally synchronized with the external MCLK

clock, and the resultant synchronous signal is output on the

GPIO1 pin.

The GPIO1 and GPIO0 pins must be externally connected.

If multiple AD7779 must be synchronized, the GPIO1 pin of

one device can be connected to multiple devices. This synch-

ronization method requires the use of a common MCLK signal

for all the AD7779 devices connected, as shown in Figure 108.

GPIO2

GPIO0

MCLK

GPIO1

GPIO2

MCLK

GPIO1

GPIO2

MCLK

GPIO1

AD7779

SYNCHRONIZATION

LOGIC

PULSE

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MCLK

Figure 108. Hardware ODR Update

SRC Bandwidth

The SINC filter architecture allows the user to select a noninteger

value as the decimation range This versatility means that the

filter notches must be adjusted dynamically: two notches at the

variable frequency, and one fixed notch to remove the PGA

chopping tone. Consequently, the traditional formula for the

−0.1 dB and −3 dB bandwidth must be adjusted depending on

the selected decimation rate.

The bandwidth transfer function is not linear but can be

approximated by using a linear function.

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