AD7779 datasheet(79/97 Pages) AD

79 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 79 of 97

CHANNEL 3 GAIN MIDDLE BYTE REGISTER

Address: 0x032, Reset: 0x00, Name: CH3_GAIN_MID_BYTE

Com bined gain register Channel 3

[7:0] CH3_GAIN_ALL[15:8] (R/W)

Table 93. Bit Descriptions for CH3_GAIN_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_GAIN_ALL[15:8]

Combined Gain Register Channel 3

0x0

R/W

CHANNEL 3 GAIN LOWER BYTE REGISTER

Address: 0x033, Reset: 0x00, Name: CH3_GAIN_LOWER_BYTE

Com bined gain register Channel 3

[7:0] CH3_GAIN_ALL[7:0] (R/W)

Table 94. Bit Descriptions for CH3_GAIN_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_GAIN_ALL[7:0]

Combined Gain Register Channel 3

0x0

R/W

CHANNEL 4 OFFSET UPPER BYTE REGISTER

Address: 0x034, Reset: 0x00, Name: CH4_OFFSET_UPPER_BYTE

Com bined offs et regis ter Channel 4

[7:0] CH4_OFFSET_ALL[23:16] (R/W)

Table 95. Bit Descriptions for CH4_OFFSET_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH4_OFFSET_ALL[23:16]

Combined Offset Register Channel 4

0x0

R/W

CHANNEL 4 OFFSET MIDDLE BYTE REGISTER

Address: 0x035, Reset: 0x00, Name: CH4_OFFSET_MID_BYTE

Com bined offs et regis ter Channel 4

[7:0] CH4_OFFSET_ALL[15:8] (R/W)

Table 96. Bit Descriptions for CH4_OFFSET_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH4_OFFSET_ALL[15:8]

Combined Offset Register Channel 4

0x0

R/W

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