AD7779 datasheet(51/97 Pages) AD

51 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 51 of 97

Figure 109 and Figure 110 show the correction factor for the

−0.1 dB and −3 dB bandwidth, respectively. In low power mode,

the offset must be divided by 4. For example, when the ODR =

1000, the −0.1 dB point is

BW = 0.0581 × 1000 +

9271

= 59 Hz

100

200

300

400

500

600

700

800

900

1000

ODR (kHz)

y = 0.0581x + 2.9271

Figure 109. −0.1 dB Correction Factor

ODR (kHz)

y = 0.3135x + 13.99

Figure 110. −3 dB Correction Factor

SRC Group Delay

The SRC group delay depends on the selected ODR and the

power mode, and is defined by the following equation:

Group delay =

ODR

SRC





where:

PM is a value that depends on the power mode, either 64 for

high resolution mode or 32 for low power mode.

SRC_N is the integer value of the programmed ODR.

ODR is the programmed output data rate.

Settling Time

The settling time is defined by the contribution of all the

internal stages, the filter delay, and the block calibration.

The filter delay is defined as 3/ODR. In some extreme cases, as

when an external pulse is applied, this value may increase to

4/ODR.

In high resolution mode, the calibration delay is defined as 62 ×

tMCLK, with a maximum error of 2 × tMCLK.

In low power mode, the calibration delay is defined as 121 ×

tMCLK, with a maximum error of 4 × tMCLK.

tMCLK is the modulator period and is 488 ns in high resolution

mode and 1.9 μs in low power mode.

DATA OUTPUT INTERFACE

The -Δ output data interface is defined by theCONV_SAR,

FORMAT0, and FORMAT1 pins in pin control mode at power-up.

The FORMATx pins cannot be changed dynamically. Table 18

shows the available options for pin control mode. If the device

is configured in SPI control mode, the SPI_SLAVE_MODE_

EN bit enables the SPI interface to transmit the -Δ ADC

conversion results, as shown in Table 26.

DOUT3 to DOUT0 Data Interface

Standalone Mode

In standalone mode, the AD7779 interface acts as a master.

There are three different DOUT configurations, configurable

through the FORMATx pins in pin control mode, as shown in

Figure 111 through Figure 113, or via the DOUT_FORMAT bits,

Bits[7:6], in SPI control mode, as described in Table 36.

Figure 114, Figure 115, and Figure 116 show the expected data

outputs for different DOUTx output modes.

AD7779 Datasheet(PDF) 51 Page - Analog Devices

AD7779 Datasheet(HTML) 51 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL