AD7779 datasheet(76/97 Pages) AD

76 / 97 page

AD7779

Data Sheet

Rev. 0 | Page 76 of 97

CHANNEL 1 GAIN MIDDLE BYTE REGISTER

Address: 0x026, Reset: 0x00, Name: CH1_GAIN_MID_BYTE

Com bined gain register Channel 1

[7:0] CH1_GAIN_ALL[15:8] (R/W)

Table 81. Bit Descriptions for CH1_GAIN_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH1_GAIN_ALL[15:8]

Combined Gain Register Channel 1

0x0

R/W

CHANNEL 1 GAIN LOWER BYTE REGISTER

Address: 0x027, Reset: 0x00, Name: CH1_GAIN_LOWER_BYTE

Com bined gain register Channel 1

[7:0] CH1_GAIN_ALL[7:0] (R/W)

Table 82. Bit Descriptions for CH1_GAIN_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH1_GAIN_ALL[7:0]

Combined Gain Register Channel 1

0x0

R/W

CHANNEL 2 OFFSET UPPER BYTE REGISTER

Address: 0x028, Reset: 0x00, Name: CH2_OFFSET_UPPER_BYTE

Com bined offs et regis ter Channel 2

[7:0] CH2_OFFSET_ALL[23:16] (R/W)

Table 83. Bit Descriptions for CH2_OFFSET_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_OFFSET_ALL[23:16]

Combined Offset Register Channel 2

0x0

R/W

CHANNEL 2 OFFSET MIDDLE BYTE REGISTER

Address: 0x029, Reset: 0x00, Name: CH2_OFFSET_MID_BYTE

Com bined offs et regis ter Channel 2

[7:0] CH2_OFFSET_ALL[15:8] (R/W)

Table 84. Bit Descriptions for CH2_OFFSET_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_OFFSET_ALL[15:8]

Combined Offset Register Channel 2

0x0

R/W

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