AD7779 datasheet(49/97 Pages) AD

49 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 49 of 97

-Δ OUTPUT DATA

ADC CONVERSION OUTPUT—HEADER AND DATA

The AD7779 -Δ conversion results are output on the DOUT0

to DOUT3 pins or over the SPI, depending on the selected

interface. If the DOUTx interface is selected, the AD7770 acts

as the master in the transmission. If the SPI interface is selected,

the controller is the master.

The DRDY signal indicates the end of conversion independently of

the interface selected to read back the -Δ conversion. When

the SPI is used to read back the -Δ conversion, if a new conversion

is completed (DRDY falling edge) before the previous conversion is

read back, the results from previous conversion are overwritten

and, consequently, the previous conversion data is corrupted.

For each channel, the width is 32 bits long: 8 bits for the header

and 24 bits for the -Δ conversion, as shown in Figure 106.

ADC DATA N

N – 1

24-BITS

8-BITS

DOUTx

DRDY

HEADER N

Figure 106. ADC Output—8-Bit Header + 24-Bit Conversion Data

In pin control mode, the header is fixed to the CRC while in SPI

mode, and can be selected between CRC or error headers.

CRC Header

The CRC header is the header generated in pin control mode or

in SPI mode if DOUT_HEADER_FORMAT is set.

As shown in Figure 107, the header consists of a chip error bit,

three bits for the ADC channel, as shown in Table 32, and

four bits for the CRC.

The chip error bit is set high if an error is detected in any channel,

as explained in the General Errors section. The chip error bit

remains 1 until the error disappears.

CHIP

ERROR

CHANNEL

NUMBER

CHANNEL

NUMBER

CHANNEL

NUMBER

CRC

Figure 107. CRC Header

Table 32. Channel ID

Channel

Channel ID 2

Channel ID 1

Channel ID 0

The CRC generated is eight bits long; the CRC 4 MSBs are placed

on the header for the first channel in the pairing and the 4 LSBs

on the header of the second channel in the pairing, as shown in

Table 33. If a channel is disabled, the 24-bit output data for this

channel is 0x000000.

Table 33. 8-Bit CRC, Header Configuration (Channel 2)

Channel 2 Header

CRC7

CRC6

CRC5

CRC4

Table 34. 8-Bit CRC, Header Configuration (Channel 3)

Channel 3 Header

CRC3

CRC2

CRC1

CRC0

ERROR Header (SPI Control Mode)

In SPI control mode, the default header can be replaced by an

error header. If the -Δ conversion is read back through the SPI

interface, disable the CRC by clearing the SPI_CRC_TEST_EN bit.

If the DOUTx interface is used, clear the DOUT_HEADER_

FORMAT bit.

The error header provides information of common error sources

specific for each channel, as shown in Table 35. Modulator and

filter errors are indicated even if the checker for this error has been

specifically disabled, as described in the -Δ ADC Errors section.

Table 35. Status Header Output

Bits

Name

Description

Alert

This bit is set high if any of the enabled diagnostic functions have detected an error, including an

external clock not detected, a memory map bit flip, or an internal CRC error. This bit is not channel specific.

The bit clears if the error is no longer present.

6:4

CH_ID_[2:0]

These bits indicate which ADC channel the following conversion data came from (see Table 32).

RESET_DETECTED

This bit indicates if a reset condition occurs. This bit is not channel specific.

MODULATOR_SATURATE

This bit indicates that the modulator output 20 consecutive 0s or 1s. The bit resets automatically after

the error is no longer present.

FILTER_SATURATE

This bit indicates that the filter output is out of bounds. The bit resets automatically after the error is

no longer present.

AIN_OV_UVERROR

This bit indicates that there is an AINx± overvoltage/undervoltage condition on the inputs. This bit is

set until the appropriate register is read back and the error is no longer present.

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