AD7779 datasheet(42/97 Pages) AD

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AD7779

Data Sheet

Rev. 0 | Page 42 of 97

Table 24. Additional Disable Power-Down Blocks

Block

Notes

VCM

GENERAL_USER_CONFIG_1, Bit 5

Enable by default

Reference Buffer

BUFFER_CONFIG_1, Bits[4:3]

Precharge mode by default

Internal Reference Buffer

GENERAL_USER_CONFIG_1, Bit 4

Disable by default

-∆ Channel

CH_DISABLE, Bits[7:0]

All channels enable

SAR

GENERAL_USER_CONFIG_1, Bit 3

Disable by default

Internal Oscillator

GENERAL_USER_CONFIG_1, Bit 2

Enable by default

Power Modes

The AD7779 offers different power modes to improve the

power efficiency, high resolution and low power mode, which

can be controlled via GENERAL_USER_CONFIG_1, Bit 6. To

further reduce the power, additional blocks can be disabled

independently, as described in Table 24.

If the power mode changes, a pulse on the SYNC_IN pin is

required.

LDO Bypassing

The internal LDOs can be individually bypassed and an external

supply can be applied directly to AREG1CAP, AREG2CAP, or

DREGCAP pins. Table 25 shows the absolute minimum and

maximum supplies for these pins, as well as the associated

Table 25. LDO Bypassing

LDO

BUFFER_CONFIG_2,

Bits[2:0]1

Supply

Max (V)

Min (V)

AREG1CAP

1XX

1.9

1.85

AREG2CAP

X1X

1.9

1.85

DREGCAP

XX1

1.98

1.65

X means don’t care.

DIGITAL SPI INTERFACE

The SPI serial interface on the AD7779 consists of four signals:

CS, SDI, SCLK and SDO. A typical connection diagram of the

SPI interface is shown in Figure 100.

DSP/FPGA

AD7779

SCLK

SDI

SDO

Figure 100. SPI Control Interface—AD7779 is the SPI Slave, Digital Signal

Processor (DSP)/Field Programmable Gate Array (FPGA) is the Master

The SPI interfaces operates in Mode 0 and Mode 3, CPOL = 0,

CPHA = 0 (Mode 0) or CPOL = 1, CPHA = 1 (Mode 3).

In pin control mode, the SDI can be used to read back the -Δ

results, depending on the level of the CONV_SAR pin, as

described in Table 17.

In SPI control mode, the SPI interface transfers data into the on-

chip registers while the SDO pin reads back data from the on-chip

registers or reads the SAR or the -Δ conversions results,

depending on the selected operation mode.

The SDO data source in SPI control mode is defined by the

GENERAL_USER_CONFIG_2 and GENERAL_USER_

CONFIG_3 registers, as described in Table 26.

Table 26. SPI Operation Mode in SPI Control Mode

GENERAL_USER_

CONFIG_2, Bit 5

Setting

GENERAL_USER_

CONFIG_3, Bit 4

Setting

Mode

Internal register

-∆ data conversion

SAR conversion

In SPI control mode, there are four different levels of I/O strength

on the SDO pin, which can be selected in GENERAL_USER_

CONFIG_2, Bits[4:3], as described in Table 27.

Table 27. SDO Strength

GENERAL_USER_CONFIG_2, Bits[4:3] Setting

Mode

Nominal

Strong

Weak

Extra strong

SCLK is the serial clock input for the device. All data transfers

(on either SDO or SDI) occur with respect to this SCLK signal.

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