AD7779 datasheet(73/97 Pages) AD

73 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 73 of 97

BUFFER CONFIGURATION 2 REGISTER

Address: 0x01A, Reset: 0xC0, Name: BUFFER_CONFIG_2

Reference buffer positive precharge

enable

DRegCap Overdrive Enable.

Reference buffer negative precharge

enable

AReg2Cap Overdrive Enable

AReg1Cap Overdrive Enable

[7] REFBUFP_PREQ (R/W)

[0] PDB_DLDO_OVRDRV (R/W)

[6] REFBUFN_PREQ (R/W)

[1] PDB_ALDO2_OVRDRV (R/W)

[5:3] RESERVED

[2] PDB_ALDO1_OVRDRV (R/W)

Table 70. Bit Descriptions for BUFFER_CONFIG_2

Bits

Bit Name

Settings

Description

Reset

Access

REFBUFP_PREQ

Reference Buffer Positive Precharge Enable

0x1

R/W

REFBUFN_PREQ

Reference Buffer Negative Precharge Enable

0x1

R/W

[5:3]

RESERVED

Reserved.

0x0

R/W

PDB_ALDO1_OVRDRV

AREG1CAP Overdrive Enable

0x0

R/W

PDB_ALDO2_OVRDRV

AREG2CAP Overdrive Enable

0x0

R/W

PDB_DLDO_OVRDRV

DREGCAP Overdrive Enable

0x0

R/W

CHANNEL 0 OFFSET UPPER BYTE REGISTER

Address: 0x01C, Reset: 0x00, Name: CH0_OFFSET_UPPER_BYTE

Com bined Offset register Channel 0

[7:0] CH0_OFFSET_ALL[23:16] (R/W)

Table 71. Bit Descriptions for CH0_OFFSET_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH0_OFFSET_ALL[23:16]

Combined Offset Register Channel 0

0x0

R/W

CHANNEL 0 OFFSET MIDDLE BYTE REGISTER

Address: 0x01D, Reset: 0x00, Name: CH0_OFFSET_MID_BYTE

Com bined Offs et regis ter Channel 0

[7:0] CH0_OFFSET_ALL[15:8] (R/W)

Table 72. Bit Descriptions for CH0_OFFSET_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH0_OFFSET_ALL[15:8]

Combined Offset Register Channel 0

0x0

R/W

AD7779 Datasheet(PDF) 73 Page - Analog Devices

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