AD7779 datasheet(34/97 Pages) AD

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AD7779

Data Sheet

Rev. 0 | Page 34 of 97

MCLK

START

Σ-∆

MODULATOR

SIGNAL CHAIN FOR CHANNEL x

CONTROL BLOCK

PIN CONTROL

CONTROL

OPTION

PIN OR SPI

DIGITAL

FILTER

SINC3

SRC

GAIN

SCALING

AND

OFFSET

CORRECTION

CONVERSION

DATA INTERFACE

MODE0 TO MODE3

CS SCLK SDO SDI

SYNC_OUT

SYNC_IN

RESET

DRDY

DOUTx

SCLK

FORMAT0

AND

FORMAT1

AINx+

PGA

GAIN 1, 2, 4, 8

ESD

PROTECTION

AINx–

SPI CONTROL

Figure 91. Top Level Core Signal Chain

CORE SIGNAL CHAIN

Each -Δ ADC channel on the AD7779 has an identical signal path

from the analog input pins to the digital output pins. Figure 91

shows a top level implementation of this signal chain. Prior to

each -Δ ADC, a PGA maps sensor outputs into the ADC inputs,

providing low input current in dc (±4 nA, input current, and

±1.5 nA differential input current), an 8 pF input capacitance in

ac, and configurable gains of 1, 2, 4, and 8. See the AN-1392 for

more information. Each ADC channel has its own -Δ modulator,

which oversamples the analog input and passes the digital rep-

resentation to the digital filter block. The data is filtered, scaled

for gain and offset, and is then output on the data interface.

To minimize power consumption, the channels can be

individually disabled.

CAPACITIVE PGA

Each -Δ ADC has a dedicated PGA, offering gain ranges of 1,

2, 4, and 8. This PGA reduces the need for an external input buffer

and allows the user to amplify small sensor signals to use the

full dynamic range of the AD7779.

The PGA maximize the signal chain dynamic range for small

sensor output signals.

The AD7779 uses chopping of the PGA to minimize offset and

offset drift in the input amplifier, reducing the 1/f noise as well.

For the AD7779, the chopping frequency is set to 64 kHz for high

resolution mode, and 16 kHz for low power mode (see the AN-

1131 for more information). The chopping tone is rejected by the

SINC filter.

To minimize intermodulation effects that may cause image in

the band of interest, it is recommended to limit the input signal

bandwidth to 2/3 of the chop frequency.

The capacitive PGA common-mode voltage does not depend on

the gain, and can be any value as long as the input signal voltage

is within AVSSx + 100 mV to AVDD1x – 100 mV. See Figure 89

for the maximum common-mode voltage at maximum

differential input signals.

INTERNAL REFERENCE AND REFERENCE BUFFERS

The AD7779 integrates a 2.5 V, 10 ppm/°C typical, voltage

reference that is disabled at power-up. The buffered reference is

available at Pin 49 and offers up to 10 mA of continuous current. A

100 nF capacitor is required if the reference is enabled.

In applications where a low noise reference is required, it is

recommended to add a low-pass filter (LPF) with a cutoff

frequency (fCUTOFF) below 10 Hz to the REF_OUT pin. Connect

the output of this filter to REFx+, and connect AVSSx to REFx−.

In this scenario, config-ure the -Δ reference as external. An

example of performance with and without the output filter is

shown in Figure 92.

115

105

0.05

0.50

1.00

2.00

2.50

DIFFERENTIAL INPUT VOLTAGE (V)

VREF = INTERNAL REFERENCE

fCUTOFF = 10Hz

Figure 92. SNR Adding External LPF with VREF = Internal Reference and

fCUTOFF = 10 Hz

The AD7779 can be used with an external reference connected

between the REFx+ and REFx− pins. Recommended reference

voltage sources for the AD7779 include the ADR441 and ADR4525

family of low noise, high accuracy voltage references.

AD7779 Datasheet(PDF) 34 Page - Analog Devices

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