TAS3002 datasheet(39/74 Pages) TI

39 / 74 page

6–5

6.4.3

Wait States

If separate I2C/SMBus commands are sent too frequently, the TAS3002 device can generate a bus wait state. This

happens when the device is busy while performing smoothing operations and changing volume, bass, and treble.

The wait occurs after the bus acknowledge on the first data byte and can exceed the maximum allowable time allowed

according to the SMBus specification (worst case 200 ms).

The following is a possible bus wait state scenario:

CODE

Start

Stop

ACTUAL

Start

Wait†

Stop

† If the master does not recognize bus waiting or if the master times out on a long wait, the master must not send consecutive I2C/SMBus commands

without a time interval of 200 ms between transactions.

6.4.4

TAS3002 SMBus Readback

The TAS3002 device supports a subset of SMBus readback. When an SMBus read command is sent to the device

(LSB = high), it answers with the subaddress and the last six bytes written.

SMBus

Command

Byte

Count

SENT

Start

69h

xxh

07h

Stop

RECEIVED

Start

07h

aah

ddh

Stop

Byte

Count

Where:

xxh

= Command byte. It is a don’t care because the response contains only the subaddress and the

last six bytes of data written to the TAS3002 device.

aah

= The last subaddress accessed in the device

ddh

= Data bytes from the TAS3002 device

NOTE: Use read sequence defined in 6.3.2

TAS3002 Datasheet(PDF) 39 Page - Texas Instruments

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