TAS3002 datasheet(13/74 Pages) TI

13 / 74 page

1–5

Table 1–1. TAS3002 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CAP_PLL

Loop filter for internal phase-locked loop (PLL)

CLKSEL

Logic low selects 256fS; logic high selects 512fS MCLK

CS1

I2C address bit A0; low = 68h, high = 6Ah

DVDD

Digital power supply (3.3 V)

DVSS

Digital ground

GPI0

GPI1

GPI2

GPI3

GPI4

GPI5

Switch input terminals

IFM/S

Digital audio I/O control (low = input; high = output)

INPA

Low when analog input A is selected (will sink 4 mA)

LINA

Left channel analog input 1

LINB

Left channel analog input 2

LRCLK/O

I/O

Left/right clock input/output (output when IFM/S is high)

MCLKO

MCLK output for slave devices

No connection; Can be used as a printed circuit board routing channel

PWR_DN

Logic high places the TAS3002 device in power-down mode

RESET

Logic low resets the TAS3002 device to the initial state

RINA

Right channel analog input 1

RINB

Right channel analog input 2

SCL

I/O

I2C clock connection

SCLK/O

I/O

Shift (bit) clock input (output when IFM/S is high)

SDA

I/O

I2C data connection

SDIN1

Serial data input 1

SDIN2

Serial data input 2

SDOUT0

Serial data output from ADC

SDOUT1

Serial data output (from internal audio processing)

SDOUT2

Serial data output (a monaural mix of left and right, before processing)

TEST

Reserved manufacturing test terminal; connect to DVSS

VCOM

Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-

µF and 0.1-µF

capacitors)

VREFM

ADC minus voltage reference

VREFP

ADC plus voltage reference

VRFILT

Voltage reference low pass filter

XTALI/MCLK

Crystal or external MCLK input

XTALO

Crystal input (crystal is connected between terminals 13 and 14)

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