CS8900A datasheet(124/128 Pages) CIRRUS

124 / 128 page

124

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

9.2 Definitions

Cyclic Redundancy Check

The method used to compute the 32-bit frame check sequence (FCS).

Frame Check Sequence

The 32-bit field at the end of a frame that contains the result of the cyclic redundancy check

(CRC).

Frame

An Ethernet string of data bits that includes the Destination Address (DA), Source Address

(SA), optional length field, Logical Link Control data (LLC data), pad bits (if needed) and

Frame Check Sequence (FCS).

Individual Address

The specific Ethernet address assigned to a device attached to the Ethernet media.

Inter-Packet Gap

Time interval between packets on the Ethernet. Minimum interval is 9.6 ms.

Jabber

A condition that results when a Ethernet node transmits longer than between 20 ms and 150

ms.

Packet

An Ethernet string of data bits that includes the Preamble, Start-of-Frame Delimiter (SFD),

Destination Address (DA), Source Address (SA), optional length field, Logical Link Control

data (LLC data), pad bits (if needed) and Frame Check Sequence (FCS). A packet is a frame

plus the Preamble and SFD.

Receive Collision

A receive collision occurs when the CI+/CI- inputs are active while a packet is being received.

Applies only to the AUI.

Signal Quality Error

When transmitting on the AUI, the MAC expects to see a collision signal on the CI+/CI- pair

within 64 bit times after the end of a transmission. If no collision occurs, there is said to be an

"SQE error". Applies only to the AUI.

Slot Time

Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot

Time equals 512 bit times.

Transmit Collision

A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI-

(AUI) are active while a packet is being transmitted.

CS8900A Datasheet(PDF) 124 Page - Cirrus Logic