PXA270 datasheet(78/126 Pages) INTEL

78 / 126 page

6-14

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

AC Timing Specifications

tsdSDIS

MD<31:0> read

data input setup

time from

SDCLK<2:1> rise

TBD

——

0.5

——

0.5

——

—

tsdSDIH

MD<31:0> read

data input hold

time from

SDCLK<2:1> rise

TBD

——

1.8

——

1.8

——

—

NOTES:

1. SDCLK for SDRAM slowest period is accomplished by divide-by-2 of the 26-MHz CLK_MEM. The fastest possible SDCLK is

accomplished by configuring CLK_MEM at 104 MHz and not setting MDREFR[KxDB2].

2. SDCLK1 and SDCLK2 frequencies are configured to be CLK_MEM frequency divided by 1 or 2, depending on the bit fields

MDREFR[K1DB2] and MDREFR[K2DB2] settings.

3. These numbers are for VCC_MEM = 1.8 V +20% / –5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the

system memory buffer strength registers (BSCNTRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK<2:1>

divide-by-2 and divide-by-4 register bits MDREFR[KxDB2] clear.

4. These numbers are for VCC_MEM = 2.5 V +/– 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system

memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-

by-2 and divide-by-4 register bit MDREFR[KxDB2] clear.

5. These numbers are for VCC_MEM = 3.3 V +/– 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system

memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-

by-2 and divide-by-4 register bit MDREFR[KxDB2] clear.

6. Refer to the “Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for register configuration.

Table 6-15. SDRAM Interface AC Specifications (Sheet 2 of 2)

Symbols

Parameters

VCC_MEM =

1.8V +20% / –5%3

VCC_MEM =

2.5V +/- 10%4

VCC_MEM =

3.3V +/- 10%5

Units

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

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