PXA270 datasheet(48/126 Pages) INTEL

48 / 126 page

4-28

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

Pin Listing and Signal Definitions

4.4

Memory Controller Reset and Initialization

On reset, the SDRAM interface is disabled. Reset values for the boot ROM are determined by

BOOT_SEL (see the Intel® PXA27x Processor Family Developers Manual, Memory Controller

chapter). Boot ROM is immediately available for reading upon exit from reset, and all memory

interface control registers are available for writing.

On hardware reset, the memory pins and controller are in the state shown in Table 4-4.

Table 4-3. Signal Types

Type

Description

CMOS input

CMOS output

OCZ

CMOS output, three-stateable

ICOCZ

CMOS bidirectional, three-stateable

Analog input

Analog output

IAOA

Analog bidirectional

IAOAZ

Analog bidirectional - three-stateable

Power supply

Table 4-4. Memory Controller Pin Reset Values (Sheet 1 of 2)

Pin Name

Reset, Sleep, Standby, Deep-Sleep, Frequency

Change, and Manual Self-Refresh Mode Values

SDCLK <31:0>

0b000

SDCKE

DQM <3:0>

0b0000

nSDCS <3:2>

GPIO (memory controller drives 0b11)†

nSDCS <1:0>

0b11

nWE

nSDRAS

nSDCAS

nOE

MA <25:0>

0x0000_00001

RDnWR

MD <31:0>

0x0000_00002

nCS <0>

nCS <5:1>

GPIO (memory controller drives 0b11111)

nPIOIR

GPIO (memory controller drives high)

nPIOIW

GPIO (memory controller drives high)

PXA270 Datasheet(PDF) 48 Page - Intel Corporation

PXA270 Datasheet(HTML) 48 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL