PXA270 datasheet(66/126 Pages) INTEL

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6-2

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

AC Timing Specifications

6.2

Reset and Power Manager Timing Specifications

The processor asserts the nRESET_OUT pin in one of several different modes:

• Power-on reset

• Hardware reset

• Watchdog reset

• GPIO reset

• Sleep mode

• Deep-sleep mode

The following sections give the timing and specifications for entry into and exit from these modes.

6.2.1

Power-On Timing Specifications

Power-on reset begins when a power supply is detected on the backup battery pin, VCC_BATT,

after the processor has been powered off. A power-on reset is equivalent to a hardware reset, in that

all units are reset to the same known state as with a hardware reset. A power-on reset is a complete

and total reset that occurs only at initial power on.

The external power-supply system must enable the power supplies for the processor in a specific

sequence to ensure proper operation. Figure 6-2 shows the timing diagram for a power-on reset

sequence. Table 6-2 details the timing.

The sequence for power-on reset is as follows:

1. VCC_BATT is established, then nRESET should be de-asserted to initiate power-on reset.

2. PWR_OUT is asserted. The processor asserts nRESET_OUT.

3. The external power-control subsystem de-asserts nBATT_FAULT to signal that the main

battery is connected and not discharged.

4. The processor asserts the SYS_EN signal to enable the power supplies VCC_IO, VCC_MEM,

VCC_BB, VCC_USB, and VCC_LCD. VCC_USIM can be established at this time also but

can be independently controlled through its own control signals. VCC_IO must be established

first. The other supplies can turn on in any order, but they must all be established within

125 milliseconds of the assertion of SYS_EN.

Figure 6-1. AC Test Load

I/O

50pf

ΖΟ = 50Ω

PXA270 Datasheet(PDF) 66 Page - Intel Corporation