PXA270 datasheet(68/126 Pages) INTEL

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6-4

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

AC Timing Specifications

6.2.2

Hardware Reset Timing

The timing sequences shown in Figure 6-3 for hardware reset and the specifications in Table 6-3

and Table 6-4 assume stable power supplies at the assertion of nRESET. Follow the timings

indicated in Section 6.2.1 if the power supplies are unstable.

tsysramp

Power-on Ramp Rate for all external high

-voltage power domains

—

mV/uS

tpwrramp

Power-on Ramp Rate for all external low

-voltage power domains (including

dynamic voltage changes on

VCC_CORE)

—

mV/uS

NOTES:

1. If the OSCC[CRI] =1 then the delay from nRESET de-assertion to SYS_EN assertion is 3000mS

NOTE: This long delay is attributed to the fact that when the CRI bit is read as 1, (which indicates that the

CLK_REQ pin was floated during a hardware or power-on reset) the processor oscillator is supplied

externally. This then forces the system to wait for the 32 kHz oscillator and the 13 MHz oscillator to

stabilize.

Table 6-2. Power-On Timing Specifications (Sheet 2 of 2)(OSCC[CRI] = 0)

Symbol

Description

Min

Typical

Max

Units

Figure 6-3. Hardware Reset Timing

Table 6-3. Hardware Reset Timing Specifications (OSCC[CRI] = 0)

Symbol

Description

Min

Typical

Max

Units

Delay between nRESET asserted and

nRESET_OUT asserted

—

< 100 ns

Assertion time of nRESET

—

Delay between nRESET de-asserted and

nRESET_OUT de-asserted

256

—

265

nRESET

nRESET_OUT

NOTE: nBATT_FAULT and nVDD_FAULT must be deasserted during the reset sequence.

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