PXA270 datasheet(97/126 Pages) INTEL

97 / 126 page

Electrical, Mechanical, and Thermal Specification

6-33

Intel® PXA270 Processor

AC Timing Specifications

6.4.5

SRAM Parameters and Timing Diagrams

The following sections describe the read/write parameters and timing diagrams for SRAM

interfaces with the memory controller.

6.4.5.1

SRAM Read Parameters and Timing Diagrams

The timing for a read access is identical to that for a non-burst ROM read (see Figure 6-11). The

timings listed in Table 6-16 for ROM reads are also used for SRAM reads. See Figure 6-11 and

Figure 6-14 for timings diagrams representing 16-bit SRAM transferring four, two, and one byte(s)

during read-bus tenures.

6.4.5.2

SRAM Write Parameters and Timing Diagrams

Figure 6-22 and Figure 6-23 show the timing for 32-bit and 16-bit SRAM writes. Table 6-19 lists

the timings used in Figure 6-22 and Figure 6-23.

Figure 6-21. 16-Bit Flash Write Timing

addr

0b0

Bytes 1:0

0b00

tflashCD

tflashDSWH

tflashWL

tflashDH

tflashCEH

tflashCES

tflashAS

Applies to:

16-bit Non-Burst Flash

16-bit Burst Flash

NOTE: MSC1[RDN2] = 2, MSC1[RDF2] = 1, MSC1[RRR2] = 2

CLK_MEM

nCS<2>

MA<25:1>

MA<0>

nWE

nOE

RDnWR

MD<15:0>

DQM<1:0>

nADV(nSDCAS)

nCSx or nSDCSx

PXA270 Datasheet(PDF) 97 Page - Intel Corporation

PXA270 Datasheet(HTML) 97 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL