PXA270 datasheet(72/126 Pages) INTEL

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6-8

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

AC Timing Specifications

Figure 6-6. Deep-Sleep-Mode Timing

VCC_USB, VCC_IO,

VCC_BB, VCC_MEM,

VCC_LCD, VCC_USIM

VCC_CORE, VCC_SRAM,

VCC_PLL

NORMAL

SYS_EN

PWR_EN

nVDD_FAULT

nRESET_OUT

Wakeup Event

DEEP SLEEP (ENTRY)

DEEP SLEEP

DEEP SLEEP (EXIT)

Intel® PXA27x State:

Tdentry

Tdexit

Tdpwr_delay

Deep-Sleep Command

Tdsys_delay

Tenable

Table 6-7. Deep-Sleep Mode Timing Specifications

Symbol

Description

Min

Typical

Max3

Units

tdentry5

Delay between deep-sleep command

issue to de-assertion of SYS_EN

0.66

—

1.661

msec

tenable

Delay between de-assertion of PWR_EN

and SYS_EN

—

usec

tdexit

Delay between wakeup event and run

mode

0.60

—

261.752,4

msec

tdsysdelay

Delay between assertion of SYS_EN to

PWR_EN2

—

125

msec

tdpwrdelay

Delay between assertion of PWR_EN to

PLL enable2

—

125

msec

NOTE: Timing specifications for nBATT_FAULT and/or nVDD_FAULT asserted deep-sleep mode entry are

below:

Fault assert

Delay between nBATT_FAULT or

nVDD_FAULT assertion (during all

modes of operation including sleep

mode) and deep-sleep mode entry6(The

de-assertion of SYS_EN defines when

the processor is in deep-sleep mode)

0.33

—

1.56

msec

NOTES:

1. -1ms if not using DC2DC

2. 0.15ms less time if exiting from Deep-sleep mode to 13M mode

3. Add 0.1ms if the wake up event is external

4. Oscillator start/crystal stable times are programmable (300uS-11mS)

NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which

counts until the oscillator is stable. (Typical stabilization is 500

µs. Maximum can be upto 5ms)

5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode

6. Assumes PMCR[BIDAE or VIDAE] bits are set to zero (default state) - The PMCR[BIDAE or VIDAE] bits

are only read by the processor if nBATT_FAULT or nVDD_FAULT signals are asserted

PXA270 Datasheet(PDF) 72 Page - Intel Corporation

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