PXA270 datasheet(92/126 Pages) INTEL

Part #	PXA270

Description	Electrical, Mechanical, and Thermal Specification

PDF	126 Pages

Scroll/Zoom	100%

Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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92 / 126 page

6-28

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

AC Timing Specifications

Figure 6-17 indicates which clock data would be latched following the assertion of

nSDCAS(ADV), depending on the configuration of the SXCNFG[SXCLx] bit field. The period in

the diagram indicated by different frequency configuration codes (Fcodes or FCCs) is equal to the

number of SDCLK0 cycles between the READ command and the clock edge on which data is

driven onto the bus.

Figure 6-17. First-Access Latency Configuration Timing

Valid Address

0b0000

Beat 0

Beat 1

Beat 2

Beat 3 Beat 4

Beat 5

Beat 0

Beat 1

Beat 2 Beat 3

Beat 4

Beat 0

Beat 1 Beat 2

Beat 3

Beat 0 Beat 1

Beat 2

Beat 0

Beat 1

Beat 0

Code 7

Code 6

Code 5

Code 4

Code 3

Code 2

NOTE: CODE = Frequency Configuration Code

SDCLK<0>

nCS<0>

MA<19:0>

nSDCAS

DQM<3:0>

MD (Code = 2)

MD (Code = 3)

MD (Code = 4)

MD (Code = 5)

MD (Code = 6)

MD (Code = 7)

PXA270 Datasheet(PDF) 92 Page - Intel Corporation

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