PXA270 datasheet(101/126 Pages) INTEL

101 / 126 page

Electrical, Mechanical, and Thermal Specification

6-37

Intel® PXA270 Processor

AC Timing Specifications

6.4.6.1

Variable Latency I/O Read Timing

Figure 6-24 shows the timing for 32-bit variable-latency I/O (VLIO) memory reads. Table 6-20

lists the timing parameters used in these diagrams.

Table 6-20. VLIO Timing

Symbols

Parameters

MIN

TYP

MAX2

Units1

Notes

tvlioAS

Address setup to nCS asserted

—

clk_mem

—

tvlioAH

Address hold from nPWE/nOE de-

asserted

MSCx[RDN]

clk_mem

—

tvlioASRW0

Address setup to nPWE/nOE

asserted (1st access)

—

clk_mem

—

tvlioASRWn

Address setup to nPWE/nOE

asserted (next access(es))

MSCx[RDN]

clk_mem

—

tvlioCES

nCS setup to nPWE/nOE asserted

—

clk_mem

—

tvlioCEH

nCS hold from nPWE/nOE de-

asserted

—

clk_mem

—

tvlioDSWH

MD/DQM setup (minimum) to nPWE

de-asserted

MSCx[RDF]+2

clk_mem

—

tvlioDH

MD/DQM hold from nPWE de-

asserted

—

clk_mem

—

tvlioDSOH

MD setup to address changing

1.5

—

clk_mem

—

tvlioDOH

MD hold from address changing

—

tvlioRDYH

RDY hold from nPWE/nOE de-

asserted

—

tvlioRWA

nPWE/nOE assert period between

writes

MSC[RDF]+1 +

Waits

31 +

Waits

clk_mem

—

tvlioRWD

nPWE/nOE de-asserted period

between writes

MSCx[RDN*2]

clk_mem

tvlioCD

nCS de-asserted after a read/write to

next nCS or nSDCS asserted

(minimum)

MSCx[RRR]*2 +

clk_mem

—

NOTES:

1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in

loading and transition direction (rise or fall).

2. Maximum values reflect the register dynamic ranges.

3. Depending on the programmed value of MSC[RDN] and the clk_mem speed, this can be a significant amount of time.

Processor does not drive the data bus during this time between transfers. If the VLIO does not drive the data bus during this

time between transfers, the data bus is not driven for this period of time. If MSC[RDN] is programmed to 60 (which equals 60

CLK_MEM cycles), then the data bus could potentially not be driven for 30*2 = 60 CLK_MEM cycles.

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