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WM8994 Datasheet(PDF) 139 Page - Wolfson Microelectronics plc

Part # WM8994
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  359 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8994 Datasheet(HTML) 139 Page - Wolfson Microelectronics plc

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Production Data
WM8994
w
PD, April 2012, Rev 4.4
139
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R35 (0023h)
SPKMIXR
Attenuation
8
SPKOUT_CLASSAB
0
Speaker Class AB Mode Enable
0 = Class D mode
1 = Class AB mode
R37 (0025h)
ClassD
5:3
SPKOUTL_BOOST
[2:0]
000
(1.0x)
Left Speaker Gain Boost
000 = 1.00x boost (+0dB)
001 = 1.19x boost (+1.5dB)
010 = 1.41x boost (+3.0dB)
011 = 1.68x boost (+4.5dB)
100 = 2.00x boost (+6.0dB)
101 = 2.37x boost (+7.5dB)
110 = 2.81x boost (+9.0dB)
111 = 3.98x boost (+12.0dB)
2:0
SPKOUTR_BOOST
[2:0]
000
(1.0x)
Right Speaker Gain Boost
000 = 1.00x boost (+0dB)
001 = 1.19x boost (+1.5dB)
010 = 1.41x boost (+3.0dB)
011 = 1.68x boost (+4.5dB)
100 = 2.00x boost (+6.0dB)
101 = 2.37x boost (+7.5dB)
110 = 2.81x boost (+9.0dB)
111 = 3.98x boost (+12.0dB)
R34 (0022h)
SPKMIXL
Attenuation
8
SPKAB_REF_SEL
0
Selects Reference for Speaker in
Class AB mode
0 = SPKVDD/2
1 = VMID
R1825
(0721h)
Pull Control
(2)
1
SPKMODE_PU
1
SPKMODE Pull-up enable
0 = Disabled
1 = Enabled
Table 74 Speaker Mode and Boost Control
Clocking of the Class D output driver is derived from SYSCLK. The clocking frequency division is
configured automatically, according to the AIFn_SR and AIFnCLK_RATE registers. (See “Clocking
and Sample Rates” for further details of the system clocks and control registers.)
The Class D switching clock is enabled whenever SPKOUTL_ENA or SPKOUTR_ENA is set,
provided also that SPKOUT_CLASSAB = 0. The frequency is as described in Table 75.
When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the Class D clock
frequency is controlled by the AIF1_SR and AIF1CLK_RATE registers.
When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the Class D clock
frequency is controlled by the AIF2_SR and AIF2CLK_RATE registers.
Note that the applicable clocks (SYSCLK, AIF1CLK or AIF2CLK) must be present and enabled when
using the speaker outputs in Class D mode.



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