WM8994 datasheet(146/359 Pages) WOLFSON

146 / 359 page

WM8994

Production Data

PD, April 2012, Rev 4.4

146

Internal pull-up and pull-down resistors may be enabled using the GPn_PU and GPn_PD fields; this

allows greater flexibility to interface with different signals from other devices. (Note that if GPn_PU

and GPn_PD are both set for any GPIO pin, then the pull-up and pull-down will be disabled.)

Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt

event. An interrupt event is triggered on the rising and falling edge of the GPIO input. The associated

interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See

“Interrupts” for more details of the Interrupt event handling.

The register fields that control the GPIO pins are described in Table 78, Table 79 and Table 80.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1792

(0700h)

GPIO1

GP1_DIR

GPIO1 Pin Direction

0 = Output

1 = Input

GP1_PU

GPIO1 Pull-Up Enable

0 = Disabled

1 = Enabled

GP1_PD

GPIO1 Pull-Down Enable

0 = Disabled

1 = Enabled

GP1_POL

GPIO1 Polarity Select

0 = Non-inverted (Active High)

1 = Inverted (Active Low)

GP1_OP_CFG

GPIO1 Output Configuration

0 = CMOS

1 = Open Drain

GP1_DB

GPIO1 Input De-bounce

0 = Disabled

1 = Enabled

GP1_LVL

GPIO1 level. Write to this bit to set

a GPIO output. Read from this bit to

read GPIO input level.

For output functions only, when

GP1_POL is set, the register

contains the opposite logic level to

the external pin.

4:0

GP1_FN [4:0]

0000

GPIO1 Pin Function

(see Table 81 for details)

Table 78 GPIO1 Control

WM8994 Datasheet(PDF) 146 Page - Wolfson Microelectronics plc

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