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WM8994 Datasheet(PDF) 175 Page - Wolfson Microelectronics plc

Part # WM8994
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  359 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8994 Datasheet(HTML) 175 Page - Wolfson Microelectronics plc

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Production Data
WM8994
w
PD, April 2012, Rev 4.4
175
AIF1 - COMPANDING
The WM8994 supports A-law and
-law companding on both transmit (ADC) and receive (DAC) sides
of AIF1. This is configured using the register bits described in Table 92.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R769 (0301h)
AIF1 Control
(2)
4
AIF1DAC_C
OMP
0
AIF1 Receive Companding Enable
0 = Disabled
1 = Enabled
3
AIF1DAC_C
OMPMODE
0
AIF1 Receive Companding Type
0 = µ-law
1 = A-law
2
AIF1ADC_C
OMP
0
AIF1 Transmit Companding Enable
0 = Disabled
1 = Enabled
1
AIF1ADC_C
OMPMODE
0
AIF1 Transmit Companding Type
0 = µ-law
1 = A-law
Table 92 AIF1 Companding
Companding involves using a piecewise linear approximation of the following equations (as set out by
ITU-T G.711 standard) for data compression:
-law (where =255 for the U.S. and Japan):
F(x) = ln( 1 +
|x|) / ln( 1 + )
} for -1 ≤ x ≤ 1
A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
 for x ≤ 1/A
F(x) = ( 1 + lnA|x|) / (1 + lnA)
 for 1/A ≤ x ≤ 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for
-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of
data.
Companding converts 13 bits (
-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).
AIF1 8-bit mode is selected whenever AIF1DAC_COMP=1 or AIF1ADC_COMP=1. The use of 8-bit
data allows samples to be passed using as few as 8 BCLK1 cycles per LRCLK1 frame. When using
DSP mode B, 8-bit data words may be transferred consecutively every 8 BCLK1 cycles.
AIF1 8-bit mode (without Companding) may be enabled by setting AIF1DAC_COMPMODE=1 or
AIF1ADC_COMPMODE=1, when AIF1DAC_COMP=0 and AIF1ADC_COMP=0.
BIT7
BIT[6:4]
BIT[3:0]
SIGN
EXPONENT
MANTISSA
Table 93 8-bit Companded Word Composition



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