WM8994 datasheet(173/359 Pages) WOLFSON

173 / 359 page

Production Data

WM8994

PD, April 2012, Rev 4.4

173

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10:0

AIF1DAC_R

ATE [10:0]

040h

LRCLK1 Rate

LRCLK1 clock output =

BCLK1 / AIF1DAC_RATE

Integer (LSB = 1)

Valid from 8..2047

Table 89 AIF1 BCLK and LRCLK Control

AIF1 - DIGITAL AUDIO DATA CONTROL

The register bits controlling the audio data format, word length, left/right channel selection and TDM

control for AIF1 are described in Table 90.

In DSP mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A) rising edge

of BCLK following a rising edge of LRCLK (assuming default BCLK polarity). This is selected using

the AIF1_LRCLK_INV register bit, as described in Table 89.

A digital gain function is available at the audio interface input path to boost the DAC volume when a

small signal is received on DACDAT1. This is controlled using the AIF1DAC_BOOST register. To

prevent clipping, this function should not be used when the boosted data is expected to be greater

than 0dBFS.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R768 (0300h)

AIF1 Control

(1)

AIF1ADCL_

SRC

AIF1 Left Digital Audio interface source

0 = Left ADC data is output on left channel

1 = Right ADC data is output on left channel

AIF1ADCR_

SRC

AIF1 Right Digital Audio interface source

0 = Left ADC data is output on right channel

1 = Right ADC data is output on right channel

AIF1ADC_T

AIF1 transmit (ADC) TDM Control

0 = ADCDAT1 drives logic ‘0’ when not

transmitting data

1 = ADCDAT1 is tri-stated when not

transmitting data

6:5

AIF1_WL

[1:0]

AIF1 Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

Note - 8-bit modes can be selected using the

“Companding” control bits.

4:3

AIF1_FMT

[1:0]

AIF1 Digital Audio Interface Format

00 = Right justified

01 = Left justified

10 = I

2S Format

11 = DSP Mode

R769 (0301h)

AIF1 Control

(2)

AIF1DACL_

SRC

AIF1 Left Receive Data Source Select

0 = Left DAC receives left interface data

1 = Left DAC receives right interface data

AIF1DACR_

SRC

AIF1 Right Receive Data Source Select

0 = Right DAC receives left interface data

1 = Right DAC receives right interface data

WM8994 Datasheet(PDF) 173 Page - Wolfson Microelectronics plc

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