DM9008 datasheet(62/68 Pages) ETC

62 / 68 page

DM9008

ISA/Plug & Play Super Ethernet Contoller

Final

Version :DM9008-DS-F02

June 14, 2000

3. PC Board Layout Considerations

The DM9008 pinout configuration is arranged in accordance

with the pin configuration of the ISA-Bus. At the same time, the

PC board optimizes layout trace with the larger ground.

Analog Trace Routing

The cardinal rule of analog trace routing is to keep the area

enclosed by a circuit loop as small as possible to minimize the

incidence of magnetic coupling. This can conflict, however,

with the general rule of keeping trace lengths short. For

example, if circuit components are positioned along three

sides of a square, the best return route is back along the same

three sides of the square, NOT directly back along the fourth

side. This rule must be adhered to strictly. Furthermore, there

should never be an unnecessary via of feed-through inside the

circuit loop. This also implies that the circuit loop should never

encircle the power/ground planes (i.e., part of the circuit loop

above and part below these planes). This concept is illustrated

in Figure 2.

A simple case of this guideline applies to differential signal

pairs. The two traces of the pair should always be routed in

adjacent channels. To reduce capacitive coupling, each circuit

loop should be separated from the others. Circuit loops can be

separated either by physical space (if located on the same

signal layer) or by placement on signal layers on opposite

sides of the power/ground planes. The following items should

be isolated from each other.

- Receiver path

- Transmit path

- Collision path

Figure 2.

To protect the transceiver from the environment and to achieve

optimum performance, the only layout restriction for the

transmitter circuit is that the longest current path from the TXO

pin (U3, pin 15) to the coaxial cable's center conductor must be

no longer than 4 inches. The layout of the receiver circuit (U3,

pin 14), however, is critical to minimize parasitic capacitance

that can degrade the received signal. The external receiver

circuit should be isolated from power and ground planes.

Digital Trace Routing

Placement of digital components and routing of digital traces

should follow standard common-sense digital layout techniques,

such as minimizing trace lengths, daisy-chaining bus signals,

etc.

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