DM9008 datasheet(20/68 Pages) ETC

20 / 68 page

DM9008

ISA/Plug & Play Super Ethernet Contoller

Final

Version :DM9008-DS-F02

June 14, 2000

Receive Status Register (RSR)

This register records the status of the received packet,

including information on errors and the type of address match,

either physical or multicast. The contents of this register are

written to buffer memory by the DMA after reception of a good

packet. If packets with errors are to be saved, the receive

status is written to memory at the head of the erroneous packet

if an erroneous packet is received.

If packets with errors are to be rejected, the RSR will not be

written to memory. The contents will be cleared when the next

packet arrives. CRC errors, frame alignment errors and missed

packets are counted internally by DM9008, which releases the

host from reading the RSR in real time to record errors for

network management functions. The contents of this register

are not specified until after the first reception.

5432

DFR

DIS

PHY

MPA

FAE

CRC

PRX

Bit

Symbol

Description

PRX

Packet Received Intact: lndicates packet received without error. (Bits CRC, FAE, FO, and

MPA are zero for the received packet.)

CRC

CRC Error: Indicates packet received with CRC error. Increments Tally Counter (CNTR1).

This bit will also be set for Frame Alignment errors

FAE

Frame Alignment Error: Indicates that the incoming packet did not end on a byte boundary and

the CRC did not match at last byte boundary. Increments Tally counter (CNTRO)

FIFO Overrun: This bit is set when the FIFO is not serviced, causing overflow during

reception. Reception of the packet will be aborted

MPA

Missed Packet: Set when packet intended for node cannot be accepted by the DM9008

because of a lack of receive buffers, or when the controller is in monitor mode and did not

buffer the packet to memory. Increments Tally Counter (CNTR2)

PHY

Physical/Multicast Address: Indicates whether received packet had a physical or multicast

address type

0: Physical Address Match

1: Multicast/Broadcast Address Match

DIS

Receiver Disabled: Set when receiver is disabled by entering Monitor mode

Reset when receiver is re-enabled while exiting Monitor mode

DFR

Deferring: Set when the carrier or collision signal is detected by ENC. If the transceiver has

asserted the CD line as a result of the jabber, this bit will stay set, indicating the jabber

condition

Note: The following coding applies to CRC and FAE bits:

FAE

CRC

Type of Error

No error (Good CRC and <6 Dribble Bits)

CRC ERROR

Illegal, will not occur

Frame Alignment Error and CRC Error

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