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DM9008 Datasheet(PDF) 16 Page - List of Unclassifed Manufacturers |
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DM9008 Datasheet(HTML) 16 Page - List of Unclassifed Manufacturers |
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16 / 68 page ![]() DM9008 ISA/Plug & Play Super Ethernet Contoller 16 Final Version :DM9008-DS-F02 June 14, 2000 Data Configure Register (DCR) This register is used to program the DM9008 for the 8 or 16-bit memory interface, select byte ordering in 16-bit applications, and establish FIFO thresholds. The DCR must be initialized prior to loading the Remote Byte Count Registers. LAS is set on power up. 7 6 5432 1 0 -- FT1 FT0 ARM LS LAS BOS WTS Bit Symbol Description D0 WTS Word Transfer Select 0: Selects 8-bit DMA transfers 1: Selects 16-bit DMA transfers D1 BOS Byte Order Select 0: MS byte placed on SD15-SD8 and LS byte on SD7-SD0 (32000, 8086) 1: MS byte placed on SD7-SD0 and LS byte on SD15-SD8 (68000) Ignored when byte-wide DMA operation is chosen Note: Byte Order Select mode is not supported in the current version of the DM9008, so this bit should be cleared in the application D2 LAS Long Address Select 0: Dual 16-bit DMA mode 1: Single 32-bit DMA mode Note: Single 32-bit DMA mode is not supported in the current version of the DM9008, so this bit should be cleared in the application D3 LS Loopback Select 0: Loopback mode selected. Bits D1, D2 of the TCR must also be programmed for Loopback mode selected 1: Normal Operation D4 ARM Auto-initialize Remote 0: Send Command not executed, all packets removed from Buffer Ring under program control 1: Send Command executed, Remote DMA auto-initialized to remove packets from Buffer Ring D5 D6 FT0 FT1 FIFO Threshold Select: Encoded FIFO threshold. During reception, the FIFO threshold indicates the number of bytes (or words) filled into the FIFO serially from the network before received data are written to the buffer RAM Receive Thresholds FT1 FT0 Word Wide Byte Wide 0 0 1 Word 2 Bytes 0 1 2 Words 4 Bytes 1 0 4 Words 8 Bytes 1 1 6 Words 12 Bytes During transmission, the FIFO threshold indicates the number of bytes (or words filled into the FIFO from the Local DMA before transmitted data are read from the buffer RAM. Thus, the transmission threshold is 16 bytes less than the receive threshold D7 -- Reserved |
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