TMS320DM642 datasheet(34/178 Pages) TI

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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

EMIFA (64-bit) – ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or

CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the

AECLKIN

H25

IPD

AEA[20:19] pins.

AECLKIN is the default for the EMIFA input clock.

EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN,

AECLKOUT2

J23

O/Z

IPD

CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4.

EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6

AECLKOUT1

J26

O/Z

IPD

clock) frequency].

EMIFA asynchronous memory read-enable/SDRAM column-address

strobe/programmable synchronous interface-address strobe or read-enable

AARE/

•

For programmable synchronous interface, the RENEN field in the CE Space

ASDCAS/

J25

O/Z

IPU

Secondary Control Register (CExSEC) selects between ASADS and ASRE:

ASADS/ASRE

If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.

If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.

AAOE/

EMIFA asynchronous memory output-enable/SDRAM row-address

ASDRAS/

J24

O/Z

IPU

strobe/programmable synchronous interface output-enable

ASOE

AAWE/

EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable

ASDWE/

K26

O/Z

IPU

synchronous interface write-enable

ASWE

EMIFA SDRAM clock-enable (used for self-refresh mode).

ASDCKE

L25

O/Z

IPU

•

If SDRAM is not in system, ASDCKE can be used as a general-purpose

output.

EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO

ASOE3

R22

O/Z

IPU

interface)

AARDY

L22

IPU

Asynchronous memory ready input

EMIFA (64-bit) – ADDRESS

AEA22

U23

AEA21

V24

AEA20

V25

EMIFA external address (doubleword address)

AEA19

V26

EMIFA address numbering for the DM642 device starts with AEA3 to maintain

signal name compatibility with other C64x™ devices (e.g., C6414, C6415, and

AEA18

V23

C6416) [see the 64-bit EMIF addressing scheme in the TMS320C6000 DSP

AEA17

U24

External Memory Interface (EMIF) Reference Guide (literature number

SPRU266)].

AEA16

U25

Boot Configuration:

AEA15

U26

•

Controls initialization of DSP modes at reset (I) via pullup/pulldown resistors

AEA14

T24

–

Boot mode (AEA[22:21]):

AEA13

T25

00 - No boot (default mode)

O/Z

IPD

01 - HPI/PCI boot (based on PCI_EN pin)

AEA12

R23

10 - Reserved

AEA11

R24

11 - EMIFA boot

AEA10

P23

–

EMIF clock select (AEA[20:19]):

Clock mode select for EMIFA (AECLKIN_SEL[1:0])

AEA9

P24

00 - AECLKIN (default mode)

AEA8

P26

01 - CPU/4 Clock Rate

10 - CPU/6 Clock Rate

AEA7

N23

11 - Reserved

AEA6

N24

For more details, see the Device Configurations section of this data sheet.

AEA5

N26

AEA4

M23

AEA3

M24

Device Overview

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